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Possible ASIC applications and
requirements are practically endless and each application is unique, but
here is a "range finding" hypothetical exervise that may be of value in
determining if an ASIC should be considered for your project.
The hypothetical mixed-mode chip is 50% analog and 50%
digital by area, will be fabricated in a mature 25um or 0.5um CMOS mixed-mode
IC process and has the following capabilities:
| PVT: |
< 3.3V (0.25um), < 5.5V (0.5um), 200uW -
0.25W, -40C to 80C |
| Digital: |
36,000 equivalent gates (25% FF's) foundry
standard cell library |
| Analog: |
Analog processing equivalent to ten,
second order filter sections (about 20, 2 megHz GBW op-amps with
associated passive circuitry) |
| Die Size: |
2mm x 2mm (0.25um) |
4mm x 4mm (0.5um) |
Prototype Die Cost (foundry): (~40 packaged parts) |
~$24K (0.25um) |
~$12K (0.5um) |
Note: The above "Prototype Die Cost" is an
approximate cost for each foundry MPW prototype run and does not include
the ASI design fees and charges.
The preceeding exercise is intended to give a rough
idea of the capabilities and foundry prototyping costs for an IC design
targeted for a "standard" low cost CMOS process. To discuss
options for your project requirements, please call. |